View STTS75_3654369.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

june 2007 rev 7 1/38 1 STTS75 digital temperature sensor and thermal watchdog features measures temperatures from ?55c to +125c (?67f to +257f) ? 2c accuracy from ?25c to +100c (max) low operating current: 75a (typ) no external components required 2-wire i 2 c/smbus-compatible serial interface ? selectable serial bus address allows connection of up to eight devices on the same bus thermometer resolution is user-configurable from 9 (default) to 12 bits (0.5c to 0.0625c) 9-bit conversion time is 45ms (typ) programmable temperature threshold and hysteresis set points wide power supply range-operating voltage range: 2.7v to 5.5v power saving one-shot temperature measurement power up defaults permit stand-alone operation as thermostat shutdown mode to minimize power consumption separate open drain output pin operates as an interrupt or comparator/thermostat output (dual purpose event pin) packages: ?so8 ? msop8 (tssop8) (a) a. contact local st sales office for availability so8 (m) msop8 (tssop8) (ds) www.st.com
contents STTS75 2/38 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 temperature sensor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 sda (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.2 scl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.3 os /int (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.4 gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.5 a2, a1, a0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.6 v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 thermal alarm function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 fault tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 bus timeout feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 registers and register set formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.1 command/pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.3 temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.4 over-limit temperature register (t os ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.5 hysteresis temperature register (t hys ) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 power-up default conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4 2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.1 bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.2 start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
STTS75 contents 3/38 3.4.3 stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.4.4 data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4.5 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.5 read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.6 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 typical operating char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of tables STTS75 4/38 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. fault tolerance setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. shutdown mode and one-shot mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. relationship between temperature and digital output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. command/pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. register pointers selection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 7. configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 8. programmable resolution configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 10. t os and t hys register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 11. STTS75 serial bus slave addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 12. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 14. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 16. so8 ? 8-lead plastic small outline package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 33 table 17. msop8 (tssop8) ? 8-lead, thin shrink small package (3mm x 3mm) outline mechanical data 34 table 18. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STTS75 list of figures 5/38 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. connections (so8, tssop8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. typical 2-wire interface connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. os output temperature response diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 7. acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 8. slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9. typical 2-byte read from preset pointer location (e.g. temp - t os , t hys ) . . . . . . . . . . . . 24 figure 10. typical pointer set followed by an immediate read for 2-byte register (e.g. temp). . . . . . 24 figure 11. typical 1-byte read from the configuration register with preset pointer . . . . . . . . . . . . . . 24 figure 12. typical pointer set followed by an immediate read from the configuration register . . . . . 25 figure 13. configuration register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 14. t os and t hys write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 15. temperature variation vs. voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 16. bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17. so8 ? 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 18. msop8 (tssop8) ? 8-lead, thin shrink small package (3mm x 3mm) outline. . . . . . . . . . 34 figure 19. device topside marking information (so8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20. device topside marking information (msop8/tssop8). . . . . . . . . . . . . . . . . . . . . . . . . . . 36
summary description STTS75 6/38 1 summary description the STTS75 is a high-precision cmos (digital) temperature sensor ic with a delta-sigma analog-to-digital (adc) converter and an i 2 c-compatible serial di gital interface (see figure 1 on page 7 ). it is targeted for general applications such as personal computers, system thermal management, electronics equipment, and industrial controllers, and is packaged in the industry standard 8-lead tssop and so8 packages (see figure 2 on page 8 ). the device contains a band gap temperature sensor and programmable 9-to 12-bit adc which monitor and digitize the temperature to a resolution up to 0.0625c. the STTS75 is typically accurate to (3c - max) over the full temperature measurement range of ?55c to 125c with 2c accuracy in the ?25c to +100c range. at power-up, the STTS75 defaults to 9-bit resolution for software compatibility with the stlm75. STTS75 is specified for operating at supply voltages from 2.7v to 5.5v. operating at 3.3v, the supply current is typically (75a). the on-board delta sigma analog-to-digital converter (adc) converts the measured temperature to a digital value that is calibrated in c; for fahrenheit applications a lookup table or conversion routine is required. the STTS75 is factory-calibrated and requires no external components to measure temperature. 1.1 serial communications the STTS75 has a simple 2-wire i 2 c-compatible digital serial interface which allows the user to access the data in the temperature register at any time. it communicates via the serial interface with a master controller which operates at speeds up to 400khz. three pins (a0, a1, and a2) are available for address selection, and enable the user to connect up to 8 devices on the same bus without address conflict. in addition, the serial interface gives the user easy access to all STTS75 registers to customize operation of the device. 1.2 temperature sensor output the STTS75 temperature sensor has a dedicated open drain over-limit signal/alert (os /int/alert) output which features a thermal alarm function. this function provides a user-programmable trip and turn-off temperature. it can operate in either of two selectable modes: section 2.3: comparator mode , and section 2.4: interrupt mode . at power-up the STTS75 comes up in 9-bit mode and immediately begins measuring the temperature and converting the temperature to a digital value. the resolution of the digital output data is user-configurable to 9, 10, 11 , or 12 bits which correspond to temperature increments of 0.5c, 0.25c, 0.125c, and 0.0625c, respectively.
STTS75 summary description 7/38 the measured temperature value is compared with a temperature limit (which is stored in the 16-bit (t os ) read/write register), and the hysteres is temperature (which is stored in the 16-bit (t hys ) read/write register). if the measured value exceeds these limits, the os /int pin is activated (see figure 3 on page 8 ). figure 1. logic diagram 1. sda and os /int are open drain. note: see pin descriptions on page 9 for details. note: see pin descriptions on page 9 for details. ai11840 sda (1) v dd stds75 gnd scl o.s./int (1) a 0 a 1 a 2 table 1. signal names pin symbol/name type/direction description 1sda (1) 1. sda and os /int are open drain. input/ output serial data input/output 2 scl input serial clock input 3os /int (1) output over-limit signal/interrupt alert output 4 gnd supply ground ground 5a 2 input address2 input 6a 1 input address1 input 7a 0 input address0 input 8v dd supply power supply voltage (2.7v to 5.5v)
summary description STTS75 8/38 figure 2. connections (so8, tssop8) 1. sda and os /int are open drain. note: see pin descriptions on page 9 for details. figure 3. functional block diagram 1 a 2 gnd a 1 a 0 scl sda (1) v dd o.s./int (1) ai11841 2 3 4 8 7 6 5 ai11833a temperature sensor and analog-to-digital converter (adc) - a 1 a 0 v dd a 2 gnd configuration register sda scl o.s. 2-wire i 2 c interface pointer register control and logic comparator temperature register thys set point register tos set point register
STTS75 summary description 9/38 1.3 pin descriptions see figure 1 on page 7 and table 1 on page 7 for a brief overview of the signals connected to this device. 1.3.1 sda (open drain) this is the serial data input/output pin for the 2-wire serial communication port. 1.3.2 scl this is the serial clock input pin for the 2-wire serial communication port. 1.3.3 os /int (open drain) this is the over-limit signal/interrupt alert output pin. it is open drain, so it needs a pull-up resistor. note: the open drain thermostat output that indicates if the temperature has exceeded user- programmable limits (over/under temperature indicator). 1.3.4 gnd ground; it is the reference for the power supply. it must be connected to system ground. 1.3.5 a2, a1, a0 a2, a1, and a0 are selectable address pins for the 3lsbs of the i 2 c interface address. they can be set to v dd or gnd to provide 8 unique address selections. 1.3.6 v dd this is the supply voltage pin, and ranges from +2.7v to +5.5v.
operation STTS75 10/38 2 operation after each temperature measurement and analog-to-digital conversion, the STTS75 stores the temperature as a 16-bit two?s complement number in the 2-byte temperature register. the most significant bit (s, bit 15) indicates if the temperature is positive or negative: for positive numbers s = 0, and for negative numbers s = 1. the most recently converted digital measurement can be read from the temperature register at any time. since temperature conversions are performed in the background, reading the temperature register does not affect the operation in progress. bits 3 through 0 of the temperature register are hardwired to logic '0.' when the STTS75 is configured for 12-bit resolution, the 12msbs (bits 15 through 4) of the temperature register will contain temperature data. for 11-bit resolution, the 11msbs (bits 15 through 5) of the temperature register will contain data, and bi t 4 will read out as logic '0.' for 10-bit resolution, the 10msbs (bits 15 through 6) will contain data, and for 9-bit resolution the 9msbs (bits 15 through 7) will contain data and all unused l sbs will contain '0s.' table 4 on page 15 gives examples of 12-bit resolution digital output data and the corresponding temperatures. the data is compared to the values in the t os and t hys registers, and then the os /int is updated based on the result of the comparison and the operating mode. the number of t os and t hys bits used during the thermostat comparison is equal to the conversion resolution set by the ft1 and ft0 bits in the configuration register. for example, if the resolution is 9 bits, only the 9msbs of t os and t hys will be used by the thermostat comparator. the alarm fault tolerance is controlled by the fti and fto bits in the configuration register. they are used to set up a fault queue. this prevents false tripping of the os /int pin when the STTS75 is used in a noisy environment (see ta b l e 2 o n page 14 ). the STTS75 also supports a special one-s hot mode feature that performs a single temperature measurement and returns to shutdown mode. this is especially useful for low- power applications. this features is accessed by first putting the device in shutdown mode, then enabling the one-shot mode (osm) bit in the configuration register. the active state of the os /int output can be changed via the polarity (pol) bit in the configuration register. the power-up default is active-low. if the user does not wish to use the ther mostat capabilities of the STTS75, the os /int output should be left floating. note: if the thermostat is not used, the t os and t hys registers can be used for general storage of system data.
STTS75 operation 11/38 2.1 applications information STTS75 digital temperature sensors are optimal for thermal management and thermal protection applications. they require no external components for operations except for pull- up resistors on scl, sda, and os /int outputs. a 0.1f bypass capacitor is recommended. the sensing device of STTS75 is the chip itself. the typical interface connection for this type of digital sensor is shown in figure 4 on page 11 . intended applications include: system thermal management computers/disk drivers electronics/test equipment power supply modules consumer products battery management fax/printers management automotive figure 4. typical 2-wire interface connection diagram 1. sda and os /int are open drain. ai11832 pull-up v dd o.s./int (1) v dd v dd master device 0.1 f STTS75 scl gnd sda (1) pull-up v dd 10k 10k 10k a 0 a 1 a 2 i 2 c address = 1001000 (1001a 2 a 1 a 0 )
operation STTS75 12/38 2.2 thermal alarm function the STTS75 thermal alarm func tion provides user-programma ble thermostat capability and allows the STTS75 to function as a standalone thermostat without using the serial interface. the os /int output is the alarm output. this signal is an open drain output, and at power-up, this pin is configured with active-low polarity by default. 2.3 comparator mode in comparator mode, each time a temperature-to-digital (t-to-d) temperature conversion occurs, the new digital temperature is compared to the value stored in the t os and t hys registers. if a fault tolerance number of consecutive temperature measurements are greater than the value stored in the t os register, the os /int output will be activated. for example, if the ft1 and ft0 bits are equal to ?10? (fault tolerance = 4), four consecutive temperature measurements must exceed t os to activate the os /int output. once the os /int output is active, it will remain active until the first time the measured temperature drops below the temperature stored in the t hys register. when the thermostat is in comparator mode, the os /int can be programmed to operate with any amount of hysteresis. the os /int output becomes active when the measured temperature exceeds the t os value a consecutive number of times as defined by the ft1 and ft0 fault tolerance (ft) bits in the configuration register. the os /int then stays active when the temperature falls below the value stored in t hys register for a consecutive number of times as defined by the fault tolerance bits (ft1 and ft0). putting the device into shutdown mode does not clear os /int in comparator mode.
STTS75 operation 13/38 2.4 interrupt mode in interrupt mode, the os /int output first becomes active when the measured temperature exceeds the t os value a consecutive number of times equal to the ft value in the configuration register. once activated, the os /int can only be cleared by either putting the STTS75 into shutdown mode or by reading from any register (temperature, configuration, t os , or t hys ) on the device. once the os /int has been deactivated, it will only be reactivated when the measured temperature falls below the t hys value a consecutive number of times equal to the ft value. figure 5 illustrates typical os output temperature response for STTS75 configured to have a fault tolerance of 2. the interrupt/clear process is cyclical between t os and t hys . figure 5. os output temperature response diagram 1. this assumes that a read has occurred. note: the STTS75 is configured to have a fault tolerance of 2 in this example. (1) conversions t os temperature t hys inactive active inactive active os output - comparator mode os output - interrupt mode (1) (1) ai12224b
operation STTS75 14/38 2.5 fault tolerance for both comparator and interrupt modes, the alarm ?fault tolerance? setting plays a role in determining when the os /int output will be activated. fault tolerance refers to the number of consecutive times an error condition must be detected before the user is notified. higher fault tolerance settings can help eliminate fals e alarms caused by noise in the system. the alarm fault tolerance is controlled by the bits (bits 4 and 3) in the configuration register. these bits can be used to set the fault tolerance to 1, 2, 4, or 6 as shown in ta b l e 2 . at power-up, these bits both default to logic '0.' 2.6 shutdown mode for power-sensitive applications, the STTS75 offers a low-power shutdown mode. the sd bit in the configuration register controls shutdown mode. when sd is changed to login '1,' the conversion in progress will be completed and the result stored in the temperature register, after which the STTS75 will go into a low-power standby state. the os /int output will be cleared if the thermostat is o perating in interr upt mode and the os /int will remain unchanged in comparator mode. the 2-wire interface remains operational in shutdown mode, and writing a '0' to the sd bit returns the STTS75 to normal operation. table 2. fault tolerance setting ft1 ft0 STTS75 (consecutive faults) comments 0 0 1 power-up default 01 2 10 4 11 6 table 3. shutdown mode and one-shot mode description operational mode one-shot mode (osm) (bit 7) shutdown (sd) (bit 0) continuous conversion 0 0 shutdown (1) 1. the shutdown command needs to be progr ammed before sending a one-shot command. 01 continuous conversion 1 0 one-shot 1 1
STTS75 operation 15/38 2.7 temperature data format ta bl e 4 shows the relationship between the output digital data and the external temperature for 12-bit resolution. temperature data for temperature, t os and t hys registers is represented by 9-bit, 10-bit, 11-bit, and 12-bit depending upon the resolution bits rc1, rc0 (bits 6 and 5) in the configuration register (see table 7 on page 17 ). the default resolution is 9-bits. the left-most bit in the output data stream controls temperature polarity information for each conversion. if the sign bit is '0', the temperature is positive and of the sign bit is '1', the temperature is negative. 2.8 bus timeout feature the STTS75 supports an smsbus compatible ti meout function which will reset the serial i 2 c/smbus interface if sda is held low for a period greater than the timeout duration between a start and stop condition. if this occurs, the device will release the bus and wait for another start condition. table 4. relationship between temperature and digital output temperature digital output (hex) sign number of bits used by conversion resolution 9101112 always zero 12-bit resolution 0000 11- bit resolution 0 0000 10-bit resolution 0 0 0000 9-bit resolution 0 0 0 0000 +125c 0 111 1101 0 0 0 0 0000 7d00 +25.0625c 0 001 1001 0 0 0 1 0000 1910 +10.125c 0 000 1010 0 0 1 0 0000 0a20 +0.5c 0 000 0000 1 0 0 0 0000 0080 0c 0 000 0000 0 0 0 0 0000 0000 ?0.5c 1 111 1111 1 0 0 0 0000 ff80 ?10.25c 1 111 0101 1 1 1 0 0000 f5e0 ?25.0625c 1 110 0110 1 1 1 1 0000 e6f0 ?55c 1 100 1001 0 0 0 0 0000 c900
functional description STTS75 16/38 3 functional description the STTS75 registers have unique pointer designations which are defined in ta b l e 6 o n page 16 . whenever any read/write operation to th e STTS75 register is desired, the user must ?point? to the device register to be accessed. all of these user-accessible registers can be accessed via the digital serial interface at anytime (see serial interface on page 20 ), and they include: command register/address pointer register configuration register temperature register over-limit signal temperature register (t os ) hysteresis temperature register (t hys ) 3.1 registers and register set formats 3.1.1 command/pointer register the most significant bits (msbs) of the comm and register must always be zero. writing a '1' into any of these bits will cause the cu rrent operation to be terminated (see ta b l e 5 ). the command register retains pointer information between operations. therefore, this register only needs to be updated once for consecutive read operations from the same register. all bits in the command register default to '0' at power-up. table 5. command/pointer register format msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 000000p1p0 pointer table 6. register pointers selection summary pointer value (h) p1 p0 name description width (bits) type (r/w) power-on default comments 0000temp temperature register 16 read only n/a to store measured temperature data 01 0 1 conf configuration register 8r/w 00 0210t hys hysteresis register 16 r/w 4800 default = 75c 0311t os over- temperature shutdown 16 r/w 5000 set point for over- temperature shutdown (t os ) limit default = 80c
STTS75 functional description 17/38 3.1.2 configuration register the configuration register is used to store the device settings such as device operation mode, os /int operation mode, os /int polarity, and os /int fault queue. the configuration register allows the user to program various options such as conversion resolution (see ta b l e 8 ), thermostat fault tolerance, thermostat polarity, thermostat operating mode, and shutdown mode. the user has read/write access to all of the bits in the configuration register. the entire register is volatile and thus powers-up in its default state only. table 7. configuration register format byte msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 STTS75 osm rc1 rc0 ft1 ft0 pol m sd default00000000 keys: sd =shutdown control bit ft1 =fault tolerance1 bit m =thermostat mode (1) 1. indicates operation mode; 0 = compar ator mode, and 1 = interrupt mode (see comparator mode and interrupt mode on page 13 ). rc0 =resolution conversion0 bit pol =output polarity (2) 2. the os /int is active-low ('0'). rc1 =resolution conversion1 bit ft0 =fault tolerance0 bit osm =one-shot mode bit table 8. programmable resolution configurations rc1 rc0 resolution conversion time (max) remarks 0 0 9-bit 0.5c 85ms default resolution 0 1 10-bit 0.25c 170ms 1 0 11-bit 0.125c 340ms 1 1 12-bit 0.0625c 680ms
functional description STTS75 18/38 3.1.3 temperature register the temperature register is a two-byte (16-bit) ?read only? register (see ta bl e 9 o n page 18 ). digital temperatures from the adc are stored in the temperature register in two?s complement format, and the contents of this register are updated each time the a/d conversion is finished. the user can read data from the temperature register at any time. when a a/d conversion is completed, the new data is loaded into a comparator buffer to evaluate fault conditions, and will update the temper ature register if a read cycle is not ongoing. the STTS75 is continuously evaluating fault conditions regardless of read or write activity on the bus. if a read is ongoing, the previous temperature will be read. the read able temperature will be updated upon the completion of the next a/d conversion that is not masked by a read cycle. depending on the a/d conversion resolution, the 9-, 10-, 11- or 12-bit msbs of the register will contain temperature data. all unused bits following the digital temperature will be zero. the msb (bit 15) of the temperature register denotes whether the temperature data is positive or negative. a '0' in bit 15 is positive and a '1' is negative. 3.1.4 over-limit temperature register (t os ) the t os register is a two-byte (16-bit) read/write register that stores the user- programmable upper trip-point temperature for the thermal alarm in two?s complement format (see table 10 on page 19 ). this register defaults to 80c at power-up (i.e., 0101 0000 0000 0000). the format of the t os register is identical to that of the temperature register. the 4 lsbs of the t os register are hardwired to zero, so data written to these re gister bits will be ignored. the msb position contains the sign bit for the digital temperature and bit14 contains the temperature msb. the resolution setting for the a/d conversion determines how many bits of the t os register are used by the thermal alarm. for example, for 9-bit conversions, the trip-point temperature is defined by the 9 msbs of the t os register, and all remaining bits are ?don?t cares.? table 9. temperature register format bytes ms byte ls byte bits msb thsb tlsb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STTS75 sb tmsb td td td td td td 9-bit lsb 10-bit lsb 11-bit lsb 12-bit lsb 000 0 keys: sb =two?s complement sign bit tmsb =temperature msb tlsb =temperature lsb td =temperature data
STTS75 functional description 19/38 3.1.5 hysteresis temperature register (t hys ) t hys register is a two-byte (16-bit) read/write register that stores the user- programmable lower trip-point temperature for the thermal alarm in two?s complement format (see ta b l e 1 0 ). this register defaults to 75c at power-up (i.e., 0100 1011 0000 0000). the format of this register is the same as that of the temperature register. the 4 lsbs of the t hys register are hardwired to zero, so data written to these bits is ignored. the msb position contains the sign bit for the digital temperature and bit14 contains the temperature msb. the resolution setting for the a/d conversion determines how many bits of the t hys register are used by the thermal alarm. for ex ample, for 9-bit conversions, the hysteresis temperature is defined by the 9 msbs of the t hys register, and all remaining bits are ?don?t cares.? 3.2 power-up default conditions the STTS75 always powers up in the following default states: thermostat mode = comparator mode polarity = active-low fault tolerance = 1 fault (i.e., relevant bits set to '0' in the configuration register) t os = 80c t hys = 75c osm = 0 (disabled) register pointer = 00 (temperature register) conversion resolution = 9-bit (i.e., rc0 = 0 and rc1 = 0 in the configuration register; see table 7 on page 17 ) note: after power-up these conditions can be reprogrammed via the serial interface. table 10. t os and t hys register format bytes ms byte ls byte bits msb thsb tlsb lsb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 STTS75 sb tmsb td td td td td td 9-bit lsb 10-bit lsb 11-bit lsb 12-bit lsb 000 0 keys: sb =two?s complement sign bit tmsb =temperature msb tlsb =temperature lsb td =temperature data
functional description STTS75 20/38 3.3 serial interface writing to and reading from the STTS75 registers is accomplished via the two-wire serial interface protocol which requires that one devi ce on the bus initiates and controls all read and write operations. this device is called th e ?master? device. the master device also generates the scl signal which provides the clock signal for all other devices on the bus. these other devices on the bus are called ?sla ve? devices. the STTS75 is a slave device (see ta b l e 1 1 ). both the master and slave devices can send and receive data on the bus. during operations, one data bit is transmitted per clock cycle. all operations follow a repeating, nine-clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ack) or not acknowledge (nack) from the receiving device. note: there are no unused clock cycles during any operation, so there must not be any breaks in the data stream and acks/nacks during data transfers. conversely, having too few clock cycles can lead to incorrect operation if an inadvertent 8-bit read from a 16-bit register occurs. 3.4 2-wire bus characteristics the bus is intended for communication between di fferent ics. it consists of two lines: a bi- directional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull-up resistor. the following protocol has been defined: data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line, while the clock line is high, will be inte rpreted as control signals. accordingly, the following bus conditions have been defined (see figure 6 on page 21 ): 3.4.1 bus not busy both data and clock lines remain high. 3.4.2 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condition. 3.4.3 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. table 11. STTS75 serial bus slave addresses msb lsb bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 0 0 1 a2 a1 a0 r/w
STTS75 functional description 21/38 3.4.4 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be changed during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start co ndition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions is not limited. the information is transmitted byte-wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? th e device that controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? figure 6. serial bus data transfer sequence ai00587 data clock data line stable data valid start condition change of data allowed stop condition
functional description STTS75 22/38 3.4.5 acknowledge each byte of eight bits is followed by one acknowledge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse (see figure 7 on page 22 ). a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must leave the data line high to enable the master to generate the stop condition. figure 7. acknowledgement sequence ai00601 data output by receiver data output by transmitter scl from master start clock pulse for acknowledgement 12 89 msb lsb
STTS75 functional description 23/38 3.5 read mode in this mode the master reads the STTS75 slave after setting the slave address (see figure 8 ). following the write mode control bit (r/w =0) and the acknowledge bit, the word address 'an' is written to the on-chip address pointer. there are two read modes: preset pointer locations (e.g. temperature, t os and t hys registers), and pointer setting (the pointer has to be set for the register that is to be read). note: the temperature register pointer is usually the default pointer. these modes are shown in the read mo de typical timing diagrams (see figure 9 , figure 10 , and figure 11 on page 24 ). figure 8. slave address location ai12226 r/w slave address start a 0 1 a2 a1 a0 10 msb lsb
functional description STTS75 24/38 figure 9. typical 2-byte read from preset pointer location (e.g. temp - t os , t hys ) figure 10. typical pointer set followed by an immediate read for 2-byte register (e.g. temp) figure 11. typical 1-byte read from the configuration register with preset pointer ai12281b 11 91 99 1 start by master address byte most significant data byte least significant data byte ack by STTS75 ack by master no ack by master stop cond. by master 0 0 1 a2 a1 a0 r d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 ai12282b 11 91 99 1 repeat start by master address byte most significant data byte least significant data byte ack by STTS75 ack by master no ack by master stop cond. by master 0 0 1 a2 a1 a0 r d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 11 99 1 start by master address byte pointer byte ack by STTS75 ack by STTS75 001a2a1a0w 000000d1d0 ai12283b 11 99 1 start by master address byte data byte ack by STTS75 no ack by master stop cond. by master 0 0 1 a2 a1 a0 r d7 d6 d5 d4 d3 d2 d1 d0
STTS75 functional description 25/38 3.6 write mode in this mode the master transmitter transmits to the STTS75 slave receiver. bus protocol is shown in figure 12 . following the start condition and slave address, a logic '0' (r/w = 0) is placed on the bus and indicates to the addr essed device that word address will follow and is to be written to the on-chip address pointer. these modes are shown in the write mo de typical timing diagrams (see figure 12 , and figure 13 , and figure 14 on page 26 ). figure 12. typical pointer set followed by an immediate read from the configuration register figure 13. configuration register write ai12279b 1919 repeat start by master ack by STTS75 no ack by STTS75 stop cond. by master 1 0 0 1 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 r/w address byte data byte 11 99 1 start by master address byte pointer byte ack by STTS75 ack by STTS75 001a2a1a0w 000000d1d0 ai12280b 11 9919 1 start by master address byte pointer byte ack by STTS75 ack by STTS75 ack by STTS75 stop cond. by master 001a2a1a0w 000000 000d4d3d2d1d0 d1 d0 configuration byte
functional description STTS75 26/38 figure 14. t os and t hys write ai12284b 1919 ack by STTS75 ack by STTS75 stop cond. by master d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 most significant data byte least significant data byte 11 99 1 start by master address byte pointer byte ack by STTS75 ack by STTS75 001a2a1a0w 000000d1d0
STTS75 typical operating characteristics 27/38 4 typical operating characteristics figure 15. temperature variation vs. voltage ?60 ?40 ?20 0 20 40 60 80 100 120 140 23456 ?20 0.5 85 110 voltage (v) temperature ( c) 125 ai12258
maximum rating STTS75 28/38 5 maximum rating stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. 1. reflow at peak temperature of 255c to 260c for < 30 seconds (total thermal budget not to exceed 180c for between 90 to 150 seconds). table 12. absolute maximum ratings symbol parameter value unit t stg storage temperature ?60 to 150 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltage v dd +0.5 v v dd supply voltage 7.0 v v out output voltage v dd + 0.5 v i o output current 10 ma p d power dissipation 320 mw
STTS75 dc and ac parameters 29/38 6 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in ta bl e 1 3 . operating and ac measurement conditions. designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 13. operating and ac measurement conditions parameter STTS75 unit supply voltage 2.7 to 5.5 v ambient operating temperature (t a ) ?55 to 125 c input rise and fall times 5ns input pulse voltages 0.2 to 0.8v dd v input and output timing reference voltages 0.3 to 0.7v dd v
dc and ac parameters STTS75 30/38 table 14. dc and ac characteristics sym description test condition (1) 1. valid for ambient operating temperature: t a = ?55 to 125c; v dd = 2.7v to 5.5v (except where noted). min typ (2) 2. typical number taken at v dd = 3.3v, t a =25c max unit v dd supply voltage t a = ?55 to +125c 2.7 5.5 v i dd v dd supply current, active temperature conversions v dd = 3.3v 75 100 a v dd supply current, communication only t a = 25c 100 a i dd1 standby supply current, serial port inactive t a = 25c 1.0 a accuracy for corresponding range 2.7v v dd 5.5v ?25c < t a < 100 2.0 c ?55c < t a < 125 3.0 c resolution 9 to 12-bit temperature data 0.5 0.0625 c 912bits t conv conversion time 94585ms 10 90 170 ms 11 180 340 ms 12 360 680 ms t os over-temperature shutdown default value 80 c t hys hysteresis default value 75 c v ol1 os /int saturation voltage (v dd = 5v) 4ma sink current 0.5 v v ih input logic high digital pins (scl, sda, a2-a0) 0.5 x v dd v dd + 0.5 v v il input logic low digital pins -0.45 0.3 x v dd v v ol2 output logic low (sda) i ol2 = 3ma 0.4 v cin capacitance 5 pf
STTS75 dc and ac parameters 31/38 figure 16. bus timing requirements sequence 1. valid for ambient operating temperature: t a = ?55 to 125c; v dd = 2.7v to 5.5v (except where noted). 2. t ransmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of scl. 3. for smbus compatibility STTS75 supports bus timeou t. holding the sda line low for a period greater than timeout duration will cause STTS75 to reset the sda li ne to the state of serial bus communication (sda high). table 15. ac characteristics sym parameter (1) min max unit f scl scl clock frequency 0 400 khz t buf time the bus must be free before a new transmission can start 1.3 s t f sda and scl fall time 300 ns t hd:dat (2) data hold time 0.9 s t hd:sta start condition hold time (after this period the first clock pulse is generated) 600 ns t high clock high period 600 ns t low clock low period 1.3 s t r sda and scl rise time 300 ns t su:dat data setup time 100 ns t su:sta start condition setup time (only relevant for a repeated start condition) 600 ns t su:sto stop condition setup time 600 ns t time-out sda low time for reset of serial interface (3) 75 325 ns ai00589 sda p tsu:sto tsu:sta thd:sta sr scl tsu:dat tf thd:dat tr thigh tlow thd:sta tbuf s p
package mechanical data STTS75 32/38 7 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com.
STTS75 package mechanical data 33/38 figure 17. so8 ? 8-lead plastic small package outline note: drawing is not to scale. so-a e1 8 ccc b e a d c 1 e h x 45? a2 k 0.25 mm l l1 a1 gauge plane table 16. so8 ? 8-lead plastic small outline package mechanical data sym mm inches typ min max typ min max a1.750.069 a1 0.10 0.25 0.004 0.010 a2 1.25 0.049 b 0.28 0.48 0.011 0.019 c 0.17 0.23 0.007 0.009 ccc 0.10 0.004 d 4.90 4.80 5.00 0.193 0.189 0.197 e 6.00 5.80 6.20 0.236 0.228 0.244 e1 3.90 3.80 4.00 0.154 0.150 0.157 e1.27? ?0.050? ? h 0.25 0.50 0.010 0.020 k 08 08 l 0.40 1.27 0.016 0.050 l1 1.04 0.041
package mechanical data STTS75 34/38 figure 18. msop8 (tssop8) ? 8-lead, thin shrink small package (3mm x 3mm) outline note: drawing is not to scale. e3_me 1 8 ccc c l e e1 d a2 a k e b 4 5 a1 l1 l2 table 17. msop8 (tssop8) ? 8-lead, thin shrink small package (3mm x 3mm) outline mechanical data sym mm inches typ min max typ min max a1.100.043 a1 0.00 0.15 0.000 0.006 a2 0.85 0.75 0.95 0.034 0.030 0.037 b 0.22 0.40 0.009 0.016 c 0.08 0.23 0.003 0.009 d 3.00 2.80 3.20 0.118 0.110 0.126 e 4.90 4.65 5.15 0.193 0.183 0.203 e1 3.00 2.80 3.10 0.118 0.110 0.122 e0.65 0.026 l 0.60 0.40 0.80 0.024 0.016 0.032 l1 0.95 0.037 l2 0.25 0.010 k 08 08 ccc 0.10 0.004
STTS75 part numbering 35/38 8 part numbering table 18. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: STTS75 m 2 f device type STTS75 package m = so8 ds = msop8 (tssop8) (1) 1. contact local st sales office for availability temperature range 2 = ?55 to 125c shipping method f = ecopack package, tape & reel e = ecopack package, tube
package marking information STTS75 36/38 9 package marking information figure 19. device topside marking information (so8) 1. traceability codes e = additional information p = plant code y = year ww = work week figure 20. device topside marking information (msop8/tssop8) 1. traceability codes p = plant code y = year ww = work week epyww (1 ) STTS75m2 ai13912 ts75 ai13913 pyww (1 )
STTS75 revision history 37/38 10 revision history table 19. revision history date revision changes 14-jun-2006 1 initial release. 22-jan-2007 2 update features (cover page), dc and ac characteristics ( ta b l e 1 4 ), package mecanical information ( figure 17 , ta b l e 1 6 , figure 18 , ta b l e 1 7 ) and part numbering ( ta b l e 1 8 ). 01-mar-2007 3 update cover page (package information); section 2: operation ; section 2.3: comparator mode ; section 2.8: bus timeout feature ; ta b l e 1 4 ; package mechanical data ( figure 18 and ta b l e 1 7 ); and part numbering ( ta b l e 1 8 ). 18-apr-2007 4 package information (dfn8) added to cover page, figure 2 , figure 19 , table 18 . added section 9: package marking information . updated ta b l e 1 2 , 13 , 15 , and 18 . 09-may-2007 5 updated cover page, figure 19 , 22 , ta b l e 1 4 , and 18 . 16-may-2007 6 updated cover page, figure 4 , section 3.1.3 , section 3.1.5 , ta b l e 8 , 14 , and 15 . 06-jun-2007 7 updated cover page, document status upgraded to full datasheet, updated figure 2 , section 7 , 8 , 9 .
STTS75 38/38 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of STTS75

	To Download STTS75 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .